Specialized hardware accelerators for machine learning (ML) tasks help bring intelligent data processing to edge devices. To fully leverage their potential, efficient mapping of the software task onto the target hardware is required. One way to achieve this is through a joint design optimization of both hardware and software. This talk presents the parameterizable ML accelerator UltraTrail and its use in the hardware/software co-design framework HANNAH. We introduce the accelerators’ architecture and show how a hardware-aware neural architecture search can be utilized to automatically search for optimal hardware configurations. The advantages of this approach over a handcrafted solution are demonstrated on an audio use case. Finally, a generator-based approach is outlined that aims at further automating the design process of such hardware accelerators to increase performance and design efficiency.
Schedule
Timezone: PDT
Hardware-aware Edge AI using the parameterizable ML accelerator UltraTrail
Paul Palomero BERNARDO, Research Assistant
University of Tübingen
Specialized hardware accelerators for machine learning (ML) tasks help bring intelligent data processing to edge devices. To fully leverage their potential, efficient mapping of the software task onto the target hardware is required. One way to achieve this is through a joint design optimization of both hardware and software. This talk presents the parameterizable ML accelerator UltraTrail and its use in the hardware/software co-design framework HANNAH. We introduce the accelerators’ architecture and show how a hardware-aware neural architecture search can be utilized to automatically search for optimal hardware configurations. The advantages of this approach over a handcrafted solution are demonstrated on an audio use case. Finally, a generator-based approach is outlined that aims at further automating the design process of such hardware accelerators to increase performance and design efficiency.
Paul Palomero BERNARDO, Research Assistant
University of Tübingen
Paul Palomero Bernardo was born in Tübingen, Germany, 1996. He received the B.S. and M.S. degrees in computer science from University of Tübingen, Tübingen, Germany, in 2017 and 2020, respectively, where he is currently pursuing the doctoral degree (Ph.D.) at the Department of Computer Science. His current research interests include neural network hardware and design optimization.
Schedule subject to change without notice.